Typical complementary metal oxide semiconductor (CMOS) logic devices place n-channel and p-channel transistors in close proximity to one another. Together with the semiconductor material forming the substrate of the integrated CMOS device, the diffused regions within the logic device can form parasitic transistors. If these parasitic transistors are biased appropriately, the transistors can effectively short the supply voltage to ground potential in a condition that is referred to as "latchup". Latchup can result in, at best, disruption of the logic processes conducted by the device and, at worst, destruction of the device. Latchup may be prevented by holding the voltage of the substrate close to the voltage level of one of the supply voltage levels which may comprise, for example, ground potential. This may be accomplished by providing low resistance current paths to ground potential electronically coupled to the semiconductor substrate material. One method used to accomplish this in prior systems is the use of a low resistance substrate having an epitaxial layer of semiconductor material formed outwardly from the low resistance layer. The use of epitaxial substrates is highly effective in preventing latchup but is a very expensive solution and is becoming more and more expensive as semiconductor wafer diameters increase. An alternate solution is the use of low resistance guard rings surrounding the n-channel devices within the integrated CMOS structure constructed on a p-type semiconductor substrate. This solution is commonly used in input/output devices where the output pins of the integrated devices are susceptible to dramatic fluctuations due to external systems. The use of guard rings is effective but is, once again, very expensive in terms of the amount of surface area that must be dedicated to the guard rings.